Complete cache hits in one cycle

Problem

Cache hits currently take two cycles. This is for the following reasons:

• Rd and Wr storage registers must be reset before next cycle
• Only idle state checks for changes in wr and rd and stores them

Possible solutions

1. Reset wr and rd on all compares (but not data/addr)
2. Make compare sensitive to wr and rd on cache hit, then transition directly to the next compare state